Integrated circuits (ICs) form the basis for many electronic systems. Essentially, an integrated circuit (IC) or chip includes a vast number of transistors and other circuit elements that are formed on a single semiconductor wafer and are interconnected to implement a desired function. The complexity of these integrated circuits (ICs) requires the use of an increasing number of linked transistors and other circuit elements.
Many modern electronic systems are created through the use of a variety of different integrated circuits, where each integrated circuit (IC or chip) performs one or more specific functions. For example, computer systems include at least one microprocessor and a number of memory chips. Conventionally, each of these integrated circuits (ICs) are formed on a separate chip, packaged independently and interconnected on, for example, a printed circuit board (PCB).
In microelectronics, a wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed for example, by doping, etching, or deposition. Wafers are used in the fabrication of semiconductor devices such as integrated circuits or chips or dies. A single wafer may have a plurality of chips formed on the wafer. The wafer may be used having a plurality of chips formed therein, or the wafer may be cut to provide individual dies or chips. The wafers and chips or dies can form a stack by positioning the wafers and/or chips on top of one another. Copper bonding (Cu bonding) processes can be used to stack dies/chips at a chip-to-chip, chip-to-wafer, or wafer-to-wafer level.
As integrated circuit (IC) technology progresses, a need for a “system on a chip” in which the functionality of all of the IC devices of the system are packaged together without a conventional printed circuit board (PCB). Ideally, a computing system should be fabricated with all the necessary IC devices on a single chip. In practice, however, it is very difficult to implement a truly high-performance “system on a chip” because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits.
As a compromise, various “system modules” have been introduced that electrically connect and package integrated circuit (IC) devices which are fabricated on the same or on different semiconductor wafers. Initially, system modules have been created by simply stacking two chips, e.g., a logic and memory chip, on top of one another in an arrangement commonly referred to as chip-on-chip structure. Subsequently, multi-chip module (MCM) technology has been utilized to stack a number of chips on a common substrate to reduce the overall size and weight of the package which directly translates into reduced system size.
Existing multi-chip module (MCM) technology provides performance enhancements over single chip or chip-on-chip (COC) packaging approaches. For example, when several semiconductor chips are mounted and interconnected on a common substrate through very high density interconnects, higher silicon packaging density and shorter chip-to-chip interconnections can be achieved. In addition, low dielectric constant materials and higher wiring density can also be obtained which lead to increased system speed and reliability, reduced weight, volume, power consumption, and heat to be dissipated for the same level of performance. However, MCM approaches still suffer from additional problems, such as, bulky packaging, wire length and wire bonding that gives rise to stray inductances which interfere with the operation of the system module.
Typically, optimization of Cu bonding was achieved by utilizing one pattern density with specific bond pad dimensions and/or via dimensions. Vias and electrically connected pads refer to vias/pads with a plated hole that connects conductive tracks from one layer of a chip to another layer(s). Current solutions are not compatible with standard CMOS processes in which a variety of pattern densities and pad/via sizes may be used. Additionally, due to mechanical stability issues most of the bonding fails occur at the edge of the bonded pattern which often, in addition to degraded bonding yield, leads to corrosion issues. Additionally, for 3D applications, a method or device is needed to provide additional protection from mechanical damage (such as crack propagation, chipping, dicing, etc.) caused during the semiconductor fabrication process.
In the current state of the art, electrically active bonded pads and/or vias had to be often placed in the central location of the pattern to provide good reliability for these contacts. One major challenge of three dimensional (3-D) wafer-to-wafer vertical stack integration technology is the metal bonding between wafers and between die in a single chip, and the wafer protection from possible corrosion and contamination caused or generated, by process steps after the wafers are bonded from reaching active IC devices on the bonded wafers.
Therefore, a need exists to erect a barrier structure by the edge of bonded wafers and individual die to protect the bonded wafers and die against corrosion and contamination in a three-dimensional (3-D) wafer-to-wafer vertical stack. It would also be desirable to provide an improved metal bonding method having acceptable bonding yield and reliability without being limited to pattern density or pad/via dimensions.